作者: Aivars J. Lelis, Daniel B. Habersat, G. Lopez, J.M. McGarrity, F. Barry McLean, Neil Goldsman
摘要: We have observed instability in the threshold voltage, VT, of SiC metal-oxide
semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has
routinely been observed by us in all 4H and 6H SiC MOSFETs from three different
manufacturers—even at room temperature. A positive-bias stress, applying an electric field of
about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for
another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range
of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large
number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends
several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2.
This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps,
which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge
tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).
1317
作者: Aivars J. Lelis, Daniel B. Habersat, Ronald Green, Neil Goldsman
摘要: We have observed variations in the instability in the threshold voltage, VT, of SiC metaloxide
semiconductor field-effect transistors (MOSFETs) from various sources and/or processes due
to gate-bias stressing as a function of temperature. In some cases we see a dramatic increase in the
instability with increasing temperature, consistent with interfacial charge trapping or de-trapping.
In other cases the temperature response is very slight, and in still other cases we actually see VT
instabilities that move in the opposite direction with bias, indicating the presence of mobile ions.
807
作者: Daniel B. Habersat, Aivars J. Lelis
摘要: We have used C-V techniques to study the bias instability of 4H-SiC MOS capacitors and FETs, and compared those results to those obtained using ID-VGS. The net “back-and-forth” instability from C-V was found to exceed that of ID-VGS and matched closely with values from fast ID-VGS and midgap extrapolation, suggesting that the C-V method is more effective at measuring a “true” instability effect than ID-VGS alone. Using C-V, capacitors and large-area MOSFETs showed similar instability behavior, implying that the presence of minority carriers are not necessary to observe bias instability. One-way bias-stress C-V measurements reveal that most of the bias instability occurs under negative bias stress, whereas the opposite is observed in one-way bias stress ID-VGS measurements. Finally, post-oxidation NO annealing reduced the ΔVT bias instability for positive bias stress but does not appear to have influenced any of the other conditions.
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