通过作者查论文: Shinsuke Harada

文章题目页数

作者: Hiroshi Kono, Takuma Suzuki, Kazuto Takao, Masaru Furukawa, Makoto Mizukami, Chiharu Ota, Shinsuke Harada, Junji Senzaki, Kenji Fukuda, Takashi Shinohe
摘要: 1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.
607
作者: Shinsuke Harada, Yusuke Kobayashi, A. Kinoshita, N. Ohse, Takahito Kojima, M. Iwaya, Hiromu Shiomi, Hidenori Kitai, Shinya Kyogoku, Keiko Ariyoshi, Yasuhiko Onishi, Hiroshi Kimura
摘要: A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.
497
作者: Hiroshi Kono, Takuma Suzuki, Makoto Mizukami, Chiharu Ota, Shinsuke Harada, Junji Senzaki, Kenji Fukuda, Takashi Shinohe
摘要: Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.
987
作者: Yusuke Kobayashi, Shinsuke Harada, Hiroshi Ishimori, Shinji Takasu, Takahito Kojima, Keiko Ariyoshi, Mitsuru Sometani, Junji Senzaki, Manabu Takei, Yasunori Tanaka, Hajime Okumura
摘要: A 3.3 kV trench MOSFET with double-trench structure was demonstrated. The deep buried p-base regions were fabricated using tilt angle ion implantation into the sidewalls of the trench contacts. The distance between the trench gate and trench contact was determined through simulation, in order to optimize the trade-off between on-resistance (RonA) and the electrical field in the oxide (Eox). A tapered trench was located in the connective area between the edge termination and the active area, in order to maintain breakdown voltage. We achieved a RonA of 10.3 mWcm2 and a breakdown voltage of 3843 V and the maximum Eox at breakdown voltage was estimated to be 3.2 MV/cm.
974
作者: Shinsuke Harada, Makoto Kato, Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda, Kazuo Arai
摘要: The channel mobility in the SiC MOSFET degrades on the rough surface of the p-well formed by ion implantation. Recently, we have developed a double-epitaxial MOSFET (DEMOSFET), in which the p-well comprises two stacked epitaxially grown p-type layers and an n-type region between the p-wells is formed by ion implantation. This device exhibited a low on-resistance of 8.5 mcm2 with a blocking voltage of 600 V. In this study, to further improve the performance, we newly developed a device structure named implantation and epitaxial MOSFET (IEMOSFET). In this device, the p-well is formed by selective high-concentration p+ implantation followed by low-concentration p- epitaxial growth. The fabricated IEMOSFET with a buried channel exhibited superior characteristics to the DEMOSFET. The extremely low specific on-resistance of 4.3 mcm2 was achieved with a blocking voltage of 1100 V. This value is the lowest in the normally-off SiC MOSFETs.
1281
作者: Seiji Suzuki, Shinsuke Harada, Tsutomu Yatsuo, Ryouji Kosugi, Junji Senzaki, Kenji Fukuda
753
作者: Kazuhiro Fujikawa, Shinsuke Harada, Atsuo Ito, Tsunenobu Kimoto, Hiroyuki Matsunami
1189
作者: Kenji Fukuda, Junji Senzaki, Mitsuhiro Kushibe, Kazutoshi Kojima, Ryouji Kosugi, Seiji Suzuki, Shinsuke Harada, Takaya Suzuki, Tomoyuki Tanaka, Kazuo Arai
1057
作者: Akimasa Kinoshita, Junji Senzaki, Makoto Katou, Shinsuke Harada, Mitsuo Okamoto, Shin Ichi Nishizawa, Kenji Fukuda, Fukuyoshi Morigasa, Tomoyoshi Endou, Takuo Isii, Teruyuki Yashima
摘要: We perform rapid thermal annealing (RTA) on areas as large as 2-inch φ (diameter) at high temperature using the hybrid super RTA (HS-RTA) equipment. The HS-RTA equipment consists of an infrared annealing unit and a RF induction annealing unit in order to uniformly anneal over 2-inch φ susceptor. As a result of annealing by the HS-RTA equipment, the temperature is elevated from RT to peak temperature (~1800°C) for less than 1 min, remain stable at annealing temperature for 30s and falls from peak temperature to 1000°C within less than 20s. The temperature distributions on a 2-inch φ susceptor are ±10°C, ±33°C and ±55°C at 1565°C, 1671°C and 1752°C, respectively. Phosphorus (P) ion implanted silicon carbide (SiC) samples are used to evaluate the performance of the HS-RTA equipment. The five implanted samples placed on the 2-inch φ susceptor are annealed for 30s at 1565°C, 1671°C and 1752°C. The mean sheet resistances of the 5 samples annealed at 1565°C, 1671°C and 1752°C are 92.6Ω/􀀀, 82.6Ω/􀀀 and 75.5Ω/􀀀, respectively. The sheet resistance uniformities are 9.9%, 7.9% and 9.3%. The average roughness (Ra) is calculated from 10 μm square Atomic Force Microscopy (AFM) image. Ra values of the samples annealed at 1565°C, 1671°C and 1752°C are 2.399 nm, 2.408 nm and 3.282 nm, respectively.
803
作者: Shinsuke Harada, Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda, Kazuo Arai
摘要: In our previous study, the on-resistance of the SiC-based vertical MOSFET had been reduced in double-epitaxial MOSFET (DEMOSFET). The device exhibited an on-resistance (Rons) of 8.5 mWcm2 with a blocking voltage (Vbr) of 600 V. This study analyzed the characteristics of the DEMOSFET using a numerical simulation. The results showed the trade-off relationship between the specific on-resistance and the blocking characteristics when the concentration of the nitrogen ions increases in the surface of the n-type region between the p-wells. Specially, the specific on-resistance was drastically improved by increasing the concentration of the nitrogen ions. The thick gate oxide on the n-type region between the p-wells had an advantage to suppress the electric field in the gate oxide.
813
显示47个文章标题中的1到10个