通过关键词查论文: MOSFET

文章题目页数

作者: Jon Q. Zhang, Matthew McCain, Brett Hull, Jeff Casady, Scott Allen, John W. Palmour, Monty Hayes, Aditya Neelakantan, John Fruth
摘要: In this paper, we present our latest results on 650 V 4H-SiC DMOSFET developments for dual-side sintered power modules in electric drive vehicles. A low specific on-resistance (Rsp,on) of 1.8 mΩ⋅cm2 has been achieved on 650 V, 7 mΩ 4H-SiC DMOSFETs at 25°C, which increases to 2.4 mΩ⋅cm2 at 150°C. For the first time, the DMOSFET chip is designed specifically for use in dual-side soldering and sintering processes, and a 650 V, 1.7 mΩ SiC DMOSFET multichip half bridge power module has been built using the wirebond-free assembly. Compared to a similarly rated Si IGBT module, the conduction and switching losses were reduced by 80% and ~50%, respectively.
822
作者: Yuki Nakano, R. Nakamura, H. Sakairi, Shuhei Mitani, T. Nakamura
摘要: The trench gate structure MOSFET, with its lack of JFET resistance, is one of the structures able to achieve low on-state resistance [1,2]. In 2008, this group succeeded in fabricating 790V SiC trench MOSFETs with the lowest Ron,sp (1.7 mΩcm2) at room temperature. However these devices had issues regarding oxide destruction at the trench bottom during high drain-source voltage application. In order to improve this problem, this group developed the double-trench MOSFET structure. This structure has both source trenches and gate trenches. This paper compares two kinds of trench MOSFETs: the conventional, single trench structure and a double-trench structure. Also, the latest characteristics are presented.
1069
作者: Anucha Ruangphanit, Natthaphon Sakuna, Surasak Niemcharoen, Rangson Muanghlua
摘要: A new mismatch model of temperature and narrow channel dependence on threshold voltage of MOSFETs and the parameter extraction method are proposed. A new model is developed from spice level3 and BSIM3 model. The IDS -VGS in linear region was used with a different of channel width. The threshold voltage parameters extraction procedure is based on the measurement of the tranconductance characteristics of MOSFET in linear region. In this predicted model, the temperature coefficient for threshold voltage and the body-bias coefficient of threshold voltage of a big MOSFET at various narrow channel width of MOSFET are determined. The results show that the deviations of experimentally measured threshold voltages of both devices from the predicted model are around 3%.
984
作者: Shen Li Chen, Hsin Yang Shih
摘要: In this work, we apply the Hauser technique and combine a newer inversion layer charge model to extract the effective channel carrier mobility (μeff) and threshold voltage (Vth) of several high-voltage DDD MOSFETs with different dimensions in channel length and width. This paper proposes and demonstrates that our new method is a novel and efficient to extract the carrier mobility and threshold voltage in the DDD MOSFET, meanwhile, the extracted data is well consistent with UT model. And, only the extracted values by our new method and BCV method can clearly reflect the narrow-width effect which results from the so called LOCOS isolation technique. Therefore, it is clearly to see that our extraction technique can exactly reflect the device characteristics in high-voltage DDD MOSFETs.
1709
作者: Kevin M. Speer, Philip G. Neudeck, Mehran Mehregany
摘要: The SiC vacuum field-effect transistor (VacFET) was first reported in 2010 as a diagnostic tool for characterizing the fundamental properties of the inverted SiC semiconductor surface without confounding issues associated with thermal oxidation. In this paper, interface state densities are extracted from measurements of threshold voltage instability on a SiC VacFET and a SiC MOSFET. It is shown that removing the oxide can reduce the interface state density by more than 70%.
777
作者: Ling Sun, Yu Wei Zhou, Hong Wang, Xiang Dong Luo, Jia Yuan Guo
摘要: The relationship between the location of gate oxide breakdown in n-MOSFETs and its electrical characteristics has been studied by using TCAD software. The comparison of device terminal current with gate oxide breakdown at different locations suggests that the variation of the source and the drain currents can be directly correlated to the breakdown location in the ultra thin gate oxide. The results provide a fundamental understanding to the experimental results observed in our devices.
57
作者: Ronald Green, A.J. Lelis, M. El, Daniel B. Habersat
摘要: Although high-temperature measurements show a dramatic reduction in the bias-temperature stress-induced threshold-voltage instability of present state-of-the-art devices, a more thorough test methodology shows that several different conclusions may actually be drawn. The particular conclusion depends on the specific post-BTS measurement technique employed. Immediate room-temperature measurements suggest that significant oxide-trap activation may still be occurring. A significant, yet rapid, post-BTS recovery is observed as well. These results underline the importance of making both high-temperature and room-temperature measurements, as a function of stress and recovery time, to better ensure that the full effect of the BTS is observed. Initial AC BTS results suggest a similar level of device degradation as occurs from a DC BTS.
549
作者: Hironori Yoshioka, Takashi Nakamura, Junji Senzaki, Atsushi Shimozato, Yasunori Tanaka, Hajime Okumura, Tsunenobu Kimoto
摘要: We focused on the inability of the common high-low method to detect very fast interface states, and developed methods to evaluate such states (CψS method). We have investigated correlation between the interface state density (DIT) evaluated by the CψS method and MOSFET performance, and found that the DIT(CψS) was well reflected in MOSFET performance. Very fast interface states which are generated by nitridation restricted the improvement of subthreshold slope and field-effect mobility.
418
作者: Ivan Starkov, Stanislav Tyaginov, Hubert Enichlmair, Jong Mun Park, Hajdin Ceric, Tibor Grasser
摘要: The interface state density profile for an unstressed transistor has been carefully extracted. The experimental evidence of profile non-uniformity is presented. A scheme to separate the bulk oxide trap contribution from the total charge pumping current is suggested as an improvement to the conventional extraction procedure. The obtained information is of high importance in the context of hot-carrier degradation modeling in order to allow for a more detailed verification of the model.
267
作者: Kevin Matocha, Sujit Banerjee, Kiran Chatty
摘要: An advanced silicon carbide power MOSFET process was developed and implemented on a high-volume 150mm silicon production line. SiC power MOSFETs fabricated on this 150mm silicon production line were demonstrated with blocking voltage of 1700V with VGS=0V. These SiC MOSFETs have a specific on-resistance as low as 3.1 mΩ-cm2 at room temperature, increasing to 6.7 mΩ-cm2 at 175°C. Devices were packaged in TO-247 package and measured to have on-resistance of 45 mΩ with VGS=20V at room temperature. Clamped inductive switching characterization of these SiC MOSFETs shows turn-off losses as low as 110 uJ (700V, 19.5A). The high-temperature gate bias stability was characterized at positive (+20) and negative gate bias (-10V) at 175°C. After 750 hours of gate stress at a gate bias of VGS=+20V and 175°C, we observe less than a 250mV shift in the threshold voltage. After 750 hours of stress at VGS=-10V and 175°C, we characterize a threshold voltage shift less than 100mV. This shows promise for high-volume production of reliable SiC MOSFETs on 150mm wafers.
803
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